The invention relates to a phase locked loop system for tuning a reception frequency of a receiver for digitally modulated received signals and analog-modulated received signals such that the phase noise is minimized.
Digital television distribution services (DVB: Digital Video Broadcasting) are transmitted using an OFDM multiplexing method (OFDM: Orthogonal Frequency Division Multiplexing). The DVB transmission standard includes, inter alia, methods for a digital modulation for satellites and cable television dissemination, as well as for terrestrial dissemination, systems for video text and program information, and also for signal encryption. The OFDM multiplexing method is particularly suitable for a terrestrial distribution of digital broadcast signals which are subject to severe interference. The OFDM multiplexing method is particularly insensitive to signal echoes.
Since the signal information is coded in the signal phase in the OFDM multiplexing method, an OFDM signal receiver is particularly sensitive to phase noise and phase fluctuations. This is particularly due to the fact that the digital demodulator for OFDM demodulation is unable to compensate for phase noise which occurs above offset frequencies of 10 to 100 Hz. Conventional receivers for reception and demodulation of analog-modulated received signals are less sensitive to phase noise.
Broadcast received signals, in particular television received signals, are increasingly transmitted with digital modulation. Digital television started in Germany in summer 1996 with the pay-TV transmitter DF1. In addition to this, broadcast signals, in particular television signals, still continue to be transmitted with analog modulation. U.S. Pat. No. 5,408,202 discloses a phase locked loop having a voltage controlled oscillator, an adjustable frequency divider, a reference oscillator, a phase comparator and a loop filter. The gain of the phase comparison circuit can be adjusted via a drive circuit. The noise response is optimized as a function of the setting of the loop gain.
U.S. Pat. No. 5,631,587 discloses a frequency synthesizer with an adjustable loop bandwidth. The loop gain can be adjusted by controlling the charging current of the charge pump.
Patent Abstracts of Japan No. JP-A-11 122101 describes a phase locked loop which has a frequency divider in the feedback path as well as a reference frequency divider, with an adjustable amplifier being provided in order to improve the noise response.
Patent Abstracts of Japan No. JP-A-09 232950 discloses a PLL (Phase Locked Loop) circuit whose loop gain can be adjusted by controlling the charging current of a charge pump.
It is accordingly an object of the invention to provide a phase locked loop system which overcomes the above-mentioned disadvantages of the heretofore-known systems of this general type and in which the phase noise response is optimized.
With the foregoing and other objects in view there is provided, in accordance with the invention, a phase locked loop system for tuning a reception frequency of a receiver which receives digitally modulated signals and analog-modulated signals, the phase locked loop system includes:
at least one voltage controlled oscillator for producing an oscillator signal having an oscillator signal frequency, the oscillator signal being provided for tuning a reception frequency;
a first frequency divider, coupled to the at least one voltage controlled oscillator, for dividing the oscillator signal frequency to a nominal comparison frequency as a function of a receiving channel selection signal;
a reference oscillator for generating a reference oscillator signal having a given reference frequency;
a second frequency divider, coupled to the reference oscillator, for dividing the given reference frequency as a function of a reception mode switching signal;
a phase comparison circuit, coupled to the first frequency divider and to the second frequency divider, for comparing signals supplied by the first frequency divider and the second frequency divider in order to produce a tuning voltage for the at least one voltage-controlled oscillator, the phase comparison circuit having an adjustable gain for optimizing a phase noise;
a multiplication device, coupled to the at least one voltage controlled oscillator, for multiplying a received signal by the oscillator signal in order to produce an intermediate frequency signal; and
a detection circuit provided downstream from the multiplication device, the detection circuit detecting the phase noise on the intermediate frequency signal and generating a control signal, the adjustable gain of the phase comparison circuit being adjustable as a function of the control signal.
One advantage of the phase locked loop system according to the invention is that it is suitable for reception not only of digitally modulated broadcast received signals, but also of analog-modulated broadcast received signals.
According to the invention, a phase locked loop system for tuning the reception frequency of a receiver for digitally and analog-modulated received signals is provided, having at least one voltage controlled oscillator for producing an oscillator signal for reception frequency tuning, a first frequency divider for dividing the frequency of the oscillator signal to a nominal comparison frequency as a function of a receiving channel selection signal, a reference oscillator for emitting a reference oscillator signal at a specific reference frequency, a second frequency divider for dividing the reference frequency as a function of a reception mode switching signal, a phase comparison circuit for comparing the signals emitted from the frequency dividers in order to produce a tuning voltage for the voltage controlled oscillator, with the gain of the phase comparison circuit being adjustable in order to optimize the phase noise, in which case, the received signal can be multiplied through the use of a multiplication device by the oscillator signal in order to produce an intermediate frequency signal, the multiplication device has a phase noise detection circuit connected downstream from it in order to detect the phase noise on the intermediate frequency signal, and the gain of the phase comparison circuit is adjustable as a function of the control signal which is produced by the phase noise detection circuit.
In a preferred embodiment of the phase locked loop system according to the invention, the phase comparison circuit includes a phase comparator and a charge pump, with the gain of the phase comparison circuit being adjustable through the use of a charging current which is produced by the charge pump.
The mixer device or multiplication device preferably has an automatic gain control circuit connected downstream from it, which amplifies the received signal as a function of the amplitude of the intermediate frequency signal.
In a further advantageous embodiment of the phase locked loop system according to the invention, the charging current which is supplied by the charge pump is adjusted as a function of a control signal which is produced by a controller connected to the charge pump.
In a further advantageous embodiment of the phase locked loop system according to the invention, the first frequency divider can be switched between a plurality of frequency division ratios as a function of the receiving channel selection signal, with a frequency division ratio for receiving an analog-modulated and a digitally modulated received signal being stored, for each receiving channel which can be selected, in a memory.
In a further advantageous embodiment of the phase locked loop system according to the invention, the second frequency divider can be switched between a first frequency division ratio for an analog-modulated received signal and a second frequency division ratio for a digitally modulated received signal through the use of a switching device.
In a further advantageous embodiment of the phase locked loop system according to the invention, the tuning voltage is filtered by a loop filter.
The multiplication device preferably has at least one signal amplifier and a surface acoustic wave (SAW) signal bandpass filter connected downstream from it.
In a further advantageous embodiment of the phase locked loop system according to the invention, the reference oscillator is a quartz crystal.
The first frequency divider in the phase locked loop system according to the invention is preferably connected to a receiving channel selection device for producing the receiving channel selection signal.
In a preferred embodiment of the phase locked loop system according to the invention, the multiplication device has a phase noise detection circuit connected downstream from it, in order to detect the phase noise of the intermediate frequency signal.
The gain of the phase comparison circuit, in a preferred embodiment, is adjustable as a function of a control signal which is produced by the phase noise detection circuit.
This offers the particular advantage that the phase noise is automatically minimized as a function of the phase noise detected in the intermediate frequency signal.
According to another feature of the invention, an automatic gain control circuit is provided downstream from the multiplication device for amplifying the received signal as a function of an amplitude of the intermediate frequency signal.
According to another feature of the invention, a loop filter is coupled to the phase comparison circuit for filtering the tuning voltage produced by the phase comparison circuit.
According to yet another feature of the invention, at least one signal amplifier and a SAW bandpass filter are provided downstream of the multiplication device.
In a further preferred embodiment of the phase locked loop system according to the invention, the nominal comparison frequency is 62.5 kHz for analog-modulated received signals, and 166.7 kHz for digitally modulated received signals.
In an alternative embodiment of the phase locked loop system according to the invention, the nominal comparison frequency is 62.5 kHz for analog-modulated received signals, and 250 kHz for digitally modulated received signals.
The reference oscillator preferably produces a reference oscillator signal at a frequency of 4 MHz.
The second frequency divider can preferably be switched between a frequency division ratio of 64 for an analog-modulated received signal, and a frequency division ratio of 24 for a digitally modulated received signal.
In an alternative embodiment of the phase locked loop system according to the invention, the second frequency divider can be switched between a frequency division ratio of 64 for an analog-modulated received signal, and a frequency division ratio of 16 for a digitally modulated received signal.
In a preferred embodiment, the phase locked loop system according to the invention has a modulation type identification circuit which identifies whether the received signal is digitally modulated or analog-modulated.
The modulation type identification circuit preferably controls the switching device to switch the second frequency divider between the first frequency division ratio for an analog-modulated received signal, and the frequency division ratio for a digitally modulated received signal.
This offers the particular advantage that the switching of the frequency division ratio takes place automatically as a function of the identified modulation type.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a phase locked loop system, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.